1. Technical Field
The present invention relates in general to a method and system for efficiently accessing memory data from a memory subsystem within a data processing system and, in particular, to a store buffer implemented in a memory controller for temporarily storing recently accessed memory data. Still more particularly, the present invention relates to the memory controller having control logic for maintaining coherency between the memory controller""s store buffer and the memory subsystem in a data processing system.
2. Description of the Related Art
In shared memory multiprocessor (SMP) data processing systems, each of the multiple processors or CPU""s in the system may access and modify data stored in a shared memory. In order to synchronize access to a particular granule (e.g., cache line) of memory between multiple processors, memory read operations and memory write operations are often employed. In high-speed shared memory multiprocessor data processing systems, system performance may be limited in part by the execution time of the memory read and write operations.
A memory subsystem comprises two major elements, a memory controller and a main memory. The microprocessors or CPU""s, initiate bus cycles to the memory controller to obtain more instructions to execute or as a direct result of executing read and write instructions. In most systems, I/O devices also initiate DMA cycles to the memory controller to read or write memory. The memory controller is responsible for satisfying these requests and executing the memory read and write operations in a manner that facilitates a balanced system.
The memory controller must be particularly careful with CPU read operations. In general, CPU memory read operations stall CPU instruction execution until data has been read from memory and sent to the CPU. Most processors will implement L1 and L2 caches (auxiliary memory that provides capability through which a relatively slow main memory can interface with a CPU) in order to reduce the memory read latency. These caches can provide read data to the processing core of the microprocessors in an expeditious manner for read cycles.
In summary, memory bandwidth and memory latency are becoming increasingly critical in systems due to faster CPU operating frequencies and systems that support multiple CPUs. Moreover, the introduction of higher bandwidth I/O bus architectures such as PCI 66 MHz (Peripheral Component Interconnect) and AGP (Accelerated Graphics Port) has started to impact the CPU to memory bandwidth. These factors combined place a tremendous burden on the memory controller to supply memory data to the CPUs fast enough to keep them from stalling. Although, L1 and L2 caches are common in most system designs today which help relieve this burden on the memory controller, they do not address impacts to the memory bandwidth from direct memory access (DMA) operations and multi-processor cache-to-cache operations and multi-processor cache-to-cache communications. Therefore a need exists for a method to minimize impacts from DMA memory operations on CPU memory bandwidth, reduce latency for memory operations, and provide more efficient cache-to-cache transfers. The subject invention herein solves all these problems in a new and unique manner which has not been part of the art previously.
It is therefore one object of the present invention to provide a method and system for efficiently accessing memory data from a memory subsystem within a data processing or information handling system.
It is another object of the present invention to provide a method and system for minimizing impacts from DMA memory operations on CPU memory bandwidth and reduce latency for memory operations within a data processing or information handling system.
It is yet another object of the present invention to provide a method and system for providing more efficient cache-to-cache transfers and correct single bit errors that may occur during memory operations within a data processing or information handling system.
The foregoing objects are achieved as is now described. A store buffer is implemented in a memory controller for temporarily storing recently accessed memory data within a data processing system. The memory controller includes control logic for maintaining coherency between the memory controller""s store buffer and memory. The memory controller""s store buffer is configured into one or more arrays sufficiently mapped to handle I/O bandwidth and CPU bandwidth requirements. The combination of the store buffer and the control logic operates as a front end to the memory controller in that all memory requests are first processed by the control logic/store buffer combination for reducing memory latency and increasing effective memory bandwidth by eliminating certain memory read and write operations.
The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.